DS92LV1224TMSA

Small 28-lead SSOP package, 40MHz to 66MHz, 10 Bit Bus LVDS Deserializer

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Price:: US $0.85~1.50 / piece [Get Latest Price]

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PartNumber:: DS92LV1224TMSA

Brand:: National Semiconductor - NS | Pack: SSOP | D/C: 08+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-12-06

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Product Summary

The DS92LV1224TMSA is a 10 Bit Bus LVDS Deserializer. It receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock. Since one output transmits clock and data bits serially, the DS92LV1224TMSA eliminates clock-to-data and data-to-data skew. The powerdown pin saves power by reducing supply current when not using either device. By using the synchronization mode, the DS92LV1224TMSA will establish lock to a signal within specified lock times.

Parametrics

DS92LV1224TMSA absolute maximum ratings: (1)Supply Voltage (VCC):-0.3V to +4V; (2)CMOS/TTL Input Voltage:-0.3V to (VCC +0.3V); (3)CMOS/TTL Output Voltage:-0.3V to (VCC +0.3V); (4)Bus LVDS Receiver Input Voltage:-0.3V to +3.9V; (5)Bus LVDS Driver Output Voltage:-0.3V to +3.9V; (6)Bus LVDS Output Short Circuit Duration:10ms; (7)Junction Temperature:+150℃.

Features

DS92LV1224TMSA features: (1)Clock recovery from PLL lock to random data patterns.; (2)Guaranteed transition every data transfer cycle; (3)Chipset (Tx + Rx) power consumption < 500 mW (typ) @ 66 MHz; (4)Single differential pair eliminates multi-channel skew; (5)Flow-through pinout for easy PCB layout; (6)660 Mbps serial Bus LVDS data rate (at 66 MHz clock); (7)10-bit parallel interface for 1 byte data plus 2 control bits; (8)Synchronization mode and LOCK indicator; (9)Programmable edge trigger on clock; (10)High impedance on receiver inputs when power is off; (11)Bus LVDS serial output rated for 27Ω load; (12)Small 28-lead SSOP package.